1. Field of the Invention
The present invention relates generally to constant voltage circuits with an overcurrent protection circuit, and more particularly to a constant voltage circuit with an overcurrent protection circuit having a foldback characteristic.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional constant voltage circuit 100 having an overcurrent protection circuit with a foldback characteristic. In the following, a description of a constant voltage generation operation in the constant voltage circuit 100 is omitted, and a description is given of the overcurrent protection circuit with a foldback characteristic.
Referring to FIG. 1, the source and the gate of a p-channel MOS (PMOS) transistor M42 are connected to the source and the gate, respectively, of a PMOS transistor M41 forming a driver transistor controlling an output current iout. A drain current output from the drain of the PMOS transistor M42 is proportional to the drain current of the PMOS transistor M41.
The drain current of the PMOS transistor M42 is input to a current division circuit composed of PMOS transistors M44 and M45. The sources of the PMOS transistors M44 and M45 are connected, and the gates of the PMOS transistors M44 and M45 are connected. Accordingly, the drain current of the PMOS transistor M42 is divided into current values that are proportional to the transistor sizes of the PMOS transistors M44 and M45, and output from the PMOS transistors M44 and M45 as their respective drain currents.
The drain current of the PMOS transistor M44 flows through a resistor R53 to generate voltage across the resistor R53. When the voltage reaches the threshold voltage of an n-channel MOS (NMOS) transistor M49, the NMOS transistor M49 is turned on to switch on a PMOS transistor M43. The drain of the PMOS transistor M43 is connected to the gate of a PMOS transistor M41. Accordingly, the PMOS transistor M43 is turned on so as to raise the gate voltage of the PMOS transistor M41, so that an increase in the current iout output from the PMOS transistor M41 is controlled. As a result, the output voltage Vout of the constant voltage circuit 100, which is the voltage of an output terminal from which the current iout is output, is reduced.
The connection of resistors R51 and R52 for detecting the output voltage Vout is connected to the gate of a PMOS transistor M54, which forms an input end of a differential amplifier circuit composed of PMOS transistors M53 and M55 through M57, the PMOS transistor M54, a resistor R54, and a capacitor C51. A resistor R55 is connected between the gate of the PMOS transistor M55, which forms the other input end of the differential amplifier circuit, and a negative side supply voltage Vss. A current is supplied to the resistor R55 from a positive side supply voltage Vdd via PMOS transistors M58 and M59. Accordingly, a predetermined voltage is applied to the gate of the PMOS transistor M55.
In the differential amplifier circuit, the gate voltage of the PMOS transistor M54 is set to be higher than the gate voltage of the PMOS transistor M55 when the output voltage Vout is a predetermined voltage. When the output current iout becomes an overcurrent and flows so that the output voltage Vout is reduced, the voltage at the connection of the resistors R51 and R52 detecting the output voltage Vout is also reduced so that the gate voltage of the PMOS transistor M54 is reduced. When the gate voltage of the PMOS transistor M54 becomes lower than the gate-voltage of the PMOS transistor M55, the drain current of the PMOS transistor M54 increases so that the drain voltage of the PMOS transistor M54 increases. Since the gate of an NMOS transistor M51 is connected to the drain of the PMOS transistor M54, the NMOS transistor M51 is turned on.
When the NMOS transistor M51 is turned on, a PMOS transistor M50, which is connected to the drain of the NMOS transistor M51, is turned on. The PMOS transistor M50 forms a current mirror circuit with a PMOS transistor M52, and the PMOS transistor M52 is also turned on. The drain of the PMOS transistor M52 is connected to the gate of the PMOS transistor M41. Accordingly, when the PMOS transistor M52 is turned on, the gate voltage of the PMOS transistor M41 increases so that the drain current of the PMOS transistor M41, that is, the output current iout, is reduced. The characteristic showing the relationship between the output voltage Vout and the output current iout is a foldback characteristic as shown in FIG. 2.
For instance, according to a technique disclosed in Japanese Examined Patent Publication No. 7-46291, in the case of a decrease in output voltage due to a load short circuit or a half short, the decrease is detected in a voltage detection circuit, and an operations signal is provided from a protection circuit to a current limit circuit based on a detection signal. As a result, the current limit circuit outputs a stop signal to a control unit, so that a switching element, supplying a load with current, is maintained in a non-conducting state.
In these years, there has been a demand for power-saving electronic apparatuses, and there has also been a strong demand for a power supply circuit forming a constant voltage circuit that consumes less current. Accordingly, there has been a demand for reduction in current consumption of a protection circuit provided in the constant voltage circuit.
However, as shown in FIG. 1, the conventional overcurrent protection circuit employs a differential amplifier circuit. Therefore, when a bias current set by the PMOS transistor M53 is reduced to decrease current consumption of the differential amplifier circuit, the speed of response of the differential amplifier circuit is reduced so that it is difficult to perform phase compensation.
Inappropriate phase compensation causes a problem in that the differential amplifier circuit operates unstably to oscillate in a region where the output current iout decreases as the output voltage Vout decreases in FIG. 2. The phase compensation of the differential amplifier circuit may be performed to some extent by changing the time constants of the resistor R54 and the capacitor C51. However, it is impossible to reduce the bias current to near zero.